Modern Xilinx education emphasizes C/C++ based entry using Vitis HLS. The primer introduces how to write C-code that mimics DSP algorithms and uses "pragmas" (directives) to tell the compiler how to parallelize the code into hardware.
An introduction to the Xilinx Adaptive Compute Acceleration Platform (ACAP) or traditional FPGA fabric, focusing on: Xilinx University Program - DSP for FPGA Primer...
A significant portion of the updated Primer addresses Vivado HLS (now part of Vitis). Traditional RTL design (Verilog/VHDL) is precise but slow to iterate. HLS allows you to write C/C++ and compile it to RTL. Modern Xilinx education emphasizes C/C++ based entry using
The Primer’s Stance: "Understand RTL first, use HLS second." Traditional RTL design (Verilog/VHDL) is precise but slow
The primer includes labs where you write a C++ FIR filter, add pragmas like #pragma HLS PIPELINE or #pragma HLS UNROLL, and watch the tool generate a parallel datapath.
Key takeaway from HLS chapters: You must still understand DSP architecture. If you write a for loop and don't unroll it, HLS will synthesize a sequential, slow circuit. If you do unroll it, you get a parallel FIR. The Primer teaches you how to "think in circuits" even when writing C++.